Verification of Transaction Level Models of Embedded Systems
As complexity increases in embedded systems design, there is need for more time for verification purposes. For embedded systems, the only verification that can be done is running test cases, and the number of cases increases exponentially. In order to shorten this verification phase of the design, w...
保存先:
| 第一著者: | |
|---|---|
| フォーマット: | Online |
| 言語: | spa |
| 出版事項: |
Universidad de Costa Rica
2013
|
| 主題: | |
| オンライン･アクセス: | https://revistas.ucr.ac.cr/index.php/ingenieria/article/view/11662 |
| タグ: |
タグ追加
タグなし, このレコードへの初めてのタグを付けませんか!
|