Verification of Transaction Level Models of Embedded Systems

As complexity increases in embedded systems design, there is need for more time for verification purposes. For embedded systems, the only verification that can be done is running test cases, and the number of cases increases exponentially. In order to shorten this verification phase of the design, w...

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Detalles Bibliográficos
Autor principal: Yu Lo, Lucky Lochi
Formato: Online
Lenguaje:spa
Publicado: Universidad de Costa Rica 2013
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Acceso en línea:https://revistas.ucr.ac.cr/index.php/ingenieria/article/view/11662
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